Table of Contents
CMOS innovation is one of the most much of the time utilized advances in the semiconductor business as it tends to be effectively incorporated with ICs. At regular intervals the quantity of MOS transistors pairs on the grounds that the size of the MOSFET is decreased. Diminishing the size of the MOSFET lessens the size of the channel length which causes short channel impacts and it builds the spillage current. To diminish the short channel impacts new plans and advances are actualized. Twofold entryway MOSFET configuration has indicated improvement in execution as enhancers over a solitary MOSFET. Silicon-based MOSFET configuration can be utilized in an unforgiving domain. It has been utilized in different applications, for example, in identifying biomolecules. The expansion in number of entryways builds the current drive ability of transistors. GAA MOSFET is a case of a fourfold door around the four sides of channel that expands door power over the channel locale. It likewise increments viable channel width that improves channel current and lessens spillage current keeping short channel impacts under breaking point. Junction less MOSFET works quicker and utilizes less power with increment in ON-state current prompting a decent estimation of ION/IOFF proportion. In this article, a few door and channel built MOSFET structures are investigated and looked at for sub 45 nm innovation hub. An examination among various MOSFET structures has been made for sub threshold execution boundaries as far as IOFF, sub threshold incline and DIBL values. The simple/RF execution is examined for Tran’s conductance, compelling transistor capacitances, dependability factor and basic recurrence. The article likewise covers various uses of advance MOSFET structures in simple/computerized or IoT/biomedical applications.
A customary MOSFET keeps up its display past 100 nm. A couple of horrible effects rise in view of deduction in channel length decline dependent upon scaling patterns. Due to the scaling of microelectronic developments, the electrical execution of the device and effects of short channels should be decreased. New structures are arranged, for instance, twofold passage MOSFET, tri-portal MOSFET, multi-entryway MOSFET to compensate the effects of short channel lengths. These MOSFETs were proposed as a decision to mass MOSFET past 45 nm. Twofold passage MOSFET has various central focuses over the mass MOSFET. It reduces the short channel impacts, convergence capacitance and gives dielectric partition SOI (silicon on encasing) is moreover used in CMOS advancement on account of its quick execution and low power consumption. Envelop entryways used in MOSFET grant more channel width which extends the drive current. Capacitance model of material planned CGT has furthermore been proposed for improvement of short channel effects. Square GAA MOSFET was proposed to be used in the device test framework and can without a very remarkable stretch be participated in insignificant models. The door all around junction less MOSFET has been planned for high RF performance. ATM-DG SOI MOSFET improves RF execution, linearity and basic performance. A warm model is proposed to envision the trading of phonon in tri-portal SOI MOSFET and 3D MOSFET. DG MOSFET has been used to design intensifier for better control of short channel effects. JLDG MOSFET was proposed which lessens the short channel impacts significantly. A CSDG MOSFET was planned to store greater essentialness and addition the current stream between sources to drain. At the point when everything is said in done, the MOSFET structures are surveyed on the reason of their sub threshold execution and straightforward/RF execution. The noteworthy MOSFET limits are relied upon to be discussed before any assessment among different MOSFET structures.
Short introduction to sub-threshold
The region of action before MOSFET channel inversion is known as the sub threshold territory. The sub threshold limits are a primary factor to gain a perfect and reliable MOSFET execution.
Overview on threshold voltage
The base proportion of entryway to source voltage required for channel inversion is known as MOSFET limit voltage (Vt). The estimation of breaking point voltage depends generally on surface potential which is the voltage of MOSFET capacitor surface (top layer of polysilicon or metal over the oxide) besides, voltage in most of MOSFET.
Explanation of off and on state current
At the point when the voltage of the gate is not exactly the limit voltage the MOSFET is viewed as in OFF-state. Nonetheless, in OFF-state there is a progression of current because of minority charge bearers between the channel and source. This current is known as sub threshold current. Similarly on the other side, the point when the voltage of the gate is more than the limit voltage of the MOSFET. The MOSFET is supposed to be in ON-state. The progression of current in this state is known as ON current meant by Ion. The development of electrons happens from source to deplete.
Drain induced barrier lowering
It is a short divert impact in which edge voltage diminishes initially at high channel voltage. At the point when the length of the channel is short channel it is sufficiently close to the entryway, at high channel voltage the bottleneck opens and the transistor turns on rashly. The estimation of Drain induced barrier lowering
(DIBL) ought to be as low as conceivable to acquire perfect yield normal for MOS transistors lessening edge voltage varieties because of channel field impact on channel potential.
Structure of Device with Dimensions
The main structure of DG MOSFET is presented in Fig. 1. Here, a fully depleted tri material double gate MOSFET is used. Improvement in the RF performance, linearity and analog performance compared to the DM DG MOSFET and single material DG MOSFET.
The structure is designed in 35 nm CMOS technology. In n-MOSFET, three different gate materials of different work functions are chosen. The work function of the materials are ΦM1 = 5.0 eV, ΦM2 = 4.75 eV, ΦM3 = 4.5 eV. The material of the gate having the larger work function in place close to the source and the material which is having the lesser work function is placed close to the drain. Polysilicon gates have depletion width of polysilicon and penetration effect of dopant so metal gates are used. The thickness of the Si film is 10 nm and SiO2 is 2 nm. The concentration of dopant of the source and drain is considered to be 1020 cm–3. The ratio of the length of the three material is taken as (L1: L2: L3=1: 1: 0). The doping concentration of the substrate is taken as 1016 cm–3. Fig. 2 defines gate all around junction less MOSFET with source and drain extension to improve analog and RF performances.
In this structure, the source and drain extensions are heavily doped compared to the channel doping. The doping concentration is given as n++/n+/n++. A long channel structure is considered with film thickness of silicon less than 5 nm. The doping concentration ND=1018 cm–3, the concentration of the extension is taken as Next=1019 cm–3 , R=5 nm, L=100 nm, tox=5 nm. By including the heavily doped extensions the drain current improves. The GAAJ MOSFET having extensions has high current when compared to conventional GAAJ. The highly doped regions have increased ion current magnitude by 70%. The reliability issues concerning junction less double gate (JLDG) MOSFET are discussed in Fig. 3, the gate misalignment and thermal stability between 200 to 500 K have been studied in this article.
The gate misalignment in this structure reduces the current which in turn reduces JLDG MOSFET’s performance. The front and the back gate alignment effects the performance of the MOSFET. The effect of misalignment occurs due to the shifting of the back gate towards the source or drain side. The misalignment of gate produces non-ideal effects. The dimensions of device parameters and gate work function is 5.2 eV, the thickness of front gate oxide is 1 nm, the thickness of back gate is 1 nm, the thickness of silicon substrate 5 nm, doping concentration ND is 3 × 1019 cm–3, length of the channel L is 20 nm. Fig. 4 proposes a double step buried oxide (DSBO) SOI MOSFET.
This structure has both the advantages of bulk MOSFET and SOI structure. This structure is designed to reduce the self-heating by changing the shape of buried oxide into a double step shape for reducing the thickness of silicon dioxide. Heat exchange is easily done between the channels to substrate. In this structure there is increase in drain current irrespective of the self-heat in effects. The parameter of the device are N+ source/drain doping is 1020 cm–3, N+ source/ drain extension doping is 1019 cm–3, P-type silicon film doping is 1015 cm–3, thin-film thickness is 10 nm, raised source/drain thickness is 50 nm, oxide thickness under the source/drain is 100 nm, oxide thickness under the channel is 20 nm, channel length is 30 nm, thickness of gate oxide is 1.5 nm. In this article, two cases are taken. The first case includes the gate underlap region present at the end portion of source of the JL DG MOSFET’s as shown in Fig 5 channel region.
The second case consists of the underlapped gate region is present at the end portion of the drain of the JL DG MOSFET as depicted in Fig 6 channel region. Both types of structure are used to detect biomolecules using dielectric modulation techniques. The charged biomolecules produce an effect on the potential of the surface of JL DG MOSFET.
When the biomolecules are positively charged the surface potential move upwards and when the biomolecules are negatively charged the surface potential move downwards. The parameters of the device are, gate length 50 nm, length of the cavity 50 nm, the thickness of cavity 19 nm, thickness of channel of 20 nm, thickness of gate oxide of 10 nm, the doping in source/drain and channel is 1 × 1024 m–3, the thickness of oxide layer in open cavity region is 1 nm. A silicon-based MOSFET is declared in Fig. 7 for the improvement of operation at high temperatures.
The MOSFET is designed for harsh environmental applications. Wide band gap material is inserted locally between the regions of source and channel for high-temperature operation. The proposed SOI MOSFET structure has buried oxide (BOX) that prevents the leakage of current flowing in the substrate. The device parameters are the length of gate given as 100 nm, thickness gate oxide is 3 nm, bottom oxide thickness is 10 nm, width of barrier is 10 nm, depth of barrier 75 nm, drain and source doping and substrate are 1 × 1020 and 1 × 1017 cm–3, respectively. Fig. 8 proposes a black phosphorus junction less recessed channel MOSFET for RF application using 45 nm technology.
Black phosphorus is integrated with the junction less recessed MOSFET. In this structure drain current increases up to 0.3 mA. The OFF current reduces and there is improvement in sub threshold slope. The black phosphorus material has high ON current and low OFF current. The device parameters are length of gate is 20 nm, length of channel is 44 nm, length of drain and source region is 30 nm, device width is 200 nm, depth of groove is 38 nm, negative junction depth (NJD) is 10 nm, substrate doping is 5 × 1016 cm–3, doping of drain and source is 5 × 1016 cm–3, thickness of physical oxide is 2 nm, work function of metal is 5.16 eV, voltage of gate to source is 1.5 V, voltage of source to drain is 0.2 V. A dual material surrounded gate MOSFET of 10 nm for digital applications is explored. The advantages of DMSG MOSFET’s of 50 nm and multi-objective genetic algorithms (MOGAs) optimization technique has been combined as shown in Fig. 9.
The MOGAs approach optimizes and improves the electrical behavior of 10 nm DMSG MOSFET. This provides low power consumption and Nano scale high speed digital applications. The formula for DIBL is given as
DIBL = Vth (Vds = V) − Vth (Vds = V) Vds − Vds. (2)
The device parameters are NA is 1015 cm–3, drain and source doping is 1020 cm–3, the length L is 10 nm, the thickness of oxide is 2 nm, silicon thickness is 10 nm, L1 and L is L/2. A GC-DMGJL MOSFET (graded channel, dual material gate junction less MOSFET) is studied as shown in Fig. 10 for applications in the analog domain.
In this article GC-DMGJL performance is compared with uniform channel dual material gate junction less (UC-DMGJL) MOSFET. The GCDMGJL MOSFET gives high drain current and trans conductance and also reduces short channel effects. The device consists of high doping area Ngd = 2.5 × 1019 cm–3 near drain region of the channel, rest of the regions are uniformly doped with Nd = 2 × 1019 cm–3. The ratio of length of the metal LM1: LM2 (nm) = 15: 15. The work function of the metal is given as WM1: WM2 (eV) = 5.353: 4.8. The thickness of oxide is given as 2 nm. Length of the spacer is Wsp = 10 nm .The thickness of silicon is Tsi = 10 nm. Fig. 11 proposes a junction less metal oxide semiconductor field effective transistor structure which is capable of detecting biomolecules such as DNA, enzymes, cells, etc., using dielectric modulation technique.
Formation of a Nano gap cavity by using the process of gate oxide etching in the channel from both the sides of source and drain. The biomolecules affect the potential of the surface in the channel beneath the Nano cavity that bind the SiO2 layer present in the cavity. The dimensions of the device are tbio = 9 nm, tox1 = 1 nm, tsi = 10 nm, doping of the source, drain and channel is 1 × 1025 m–3. Length of the cavity is L1 and L3 is 25 nm, and L3 length of the oxide AL2O3 is 50 nm. A structure of 0.1 μm pocket of n-MOSFETs is discussed in Fig. 12 for applications of low voltage.
In this structure a pocket region is constructed close to the drain and source region and is heavily doped and at the center of the structure center region is constructed which is lightly doped. This design provides good immunity from short channel effects and is able to meet the specifications of OFF current and ON current. The device parameters are channel length which is 0.1 μm, the thickness of oxide is 4 nm, the junction depth (rj ) is 0.06 μm, the doping concentration of the pocket (NP ) is 1.906 × 1018 cm–3 and doping concentration in the center region (Nc ) is 2.175 × 1017 cm–3, length of the pocket (LP ) is 0.024 μm.Aa structure of Nano scale SOI MOSFET is proposed which has electrically induced source and drain extensions for suppressing short channel effects length of channel less than 50 nm and also suppresses hot electron effects. The formation of shallow drain and source by fabrication is very difficult but EJ SOI MOSFET (Fig. 13) is able to form virtual drain and source electrically.
This structure consists of triple gate, one main gate with two side gates. The biasing of side gates are independent of the main gate. These side gates form inversion layers which further forms virtual drain and source. The device parameters given are doping of silicon thin layer is 6 × 1016 cm–3, Source and drain doping is 5 × 1019 cm–3 , the side gates work function is 4.7 eV, the main gate work function is 4.9 eV, thickness of silicon thin layer is 50 nm, thickness of buried oxide is 500 nm, thickness of gate oxide is 2 nm, thickness of barrier diffusion layer is 2 nm, length of main gate is 50 nm and length of total side gate is 50 nm. The study of the surrounding gate MOSFET with dual material is presented in Fig. 14 to overcome shortchannel effects.
The parameters like threshold voltage, potential of the surface, and distribution of electric field are analytically modeled using parabolic approximation method. The comparison between DMSG and SMSG device structures having equal dimensions is taken out in terms of SCE’s. The result shows that DMSG MOSFET suppresses (SCEs) more efficiently in comparison with SMSG MOSFET. The formula for DIBL calculation is given as
DIBL = ΔVTH ΔVDS = (VTH − VTH ) (VDS − VDS ) . (3)
The work function of gold (Au ΦM1 4.8 eV), work function of cadmium (Cd) is 4.0 eV. The channel doping of p-type is 6 × 1016 cm–3, n+ source and drain doping region is 5 × 1019 cm–3. Double gate junction less MOSFET is explained in Fig. 15 using engineered gate material and source/drain extensions.
This structure is able to produce high drain current and improves RF and analog performance. The figure of merit is also increased compared to the conventional double gate junction less MOSFET. The parameters of the devices are doping concentration Nd is 5 × 1018 cm–3, doping of the extension is 5 × 1019 cm–3 , thickness of silicon tsi is 10 nm, L is 100 nm, L1 and L2 is L/2, the metal (M1 ) work function is 5.1 eV, metal (M2 ) work function is 4.5 eV. A junction less MOSFET with asymmetrical gate is shown in Fig. 16 to improve the functioning of the device.
The device has two gates with a lateral offset between them. In this structure the channel length depends upon the ON and OFF state of the MOSFET. The channel length of the MOSFET during the ON state is equal to the overlap length of the gate, and the channel length during the OFF state is combined length of the two gates minus the overlap length of the gate. This structure increases the ION to IOFF ratio and decreases the sub-threshold slope and DIBL. The structure parameters are an oxide (HfO2) with EOT 1 nm, channel doping is 1 × 1019 cm–3, length of gate is 20 nm, and thickness of silicon is 6 nm. Fig. 17 defines RF performance of the recessed channel with a transparent gate.
The values of Tran’s conductance, cut-off frequency, DIBL, and maximum oscillator frequency have been calculated. The outcomes of the structure are compared with the conventional recessed channel MOSFET. The MOSFET gate is made up of indium tin oxide which is a transparent material. The results show that there is increase of cut-off frequency by 42% and oscillator frequency is increased by132%. Due to the improvement in the gate control the short channel effects are reduced by using the transparent gate material. The length of the channel (LG) is 30 nm, width of the device is 200 nm, depth of the groove is 38 nm, junction depth of source and drain is 30 nm, Negative junction depth (NJD) is 10 nm, doping of the substrate (NA) is 1 × 1016 cm–3, doping of source and drain (ND) is 1 × 1019 cm–3, thickness of physical oxide (tox) is 2 nm. SiO2 permittivity εox is 3.9, gate to source voltage (VGS) is 0.7 V, drain to source voltage (VDS) 0.5 V, TGRC-MOSFET work function for (ΦITO) is 4.7 eV, CRCMOSFET work function (ΦM) is 4.2 eV. A structure of junction less transistor-based 6-T SRAM cell is proposed in Fig. 18 using silicon on inductor.
This structure reduces the area of the devices and increases performance. There is increase in the ION current and decrease in IOFF compared to double-gate junction less. This structure occupies only half the area of the conventional structure. Read and write operation is also improved using the proposed structure. The ratio of ION/IOFF is 106. The area of the of junction less transistor based 6-T SRAM cell using silicon on inductor is 6.9 μm2 and that of conventional structure is 11.3 μm2. The dimensions of the structure is gate length 18 nm, Tox 1 nm, Tsi channel thickness 10 nm, substrate thickness 10 nm, doping density in Substrate regions 1 × 1018 cm–3, doping density channel 1 × 1018 cm–3, work function of gate material 4.9 eV. A short channel junction less double-gate MOSFET is depicted in Fig. 19.
This structure does not contain any p-n junction because the doping of the channel is same as that of the drain and source. The RF and analog performance of the structure has been investigated. The voltage of the front and back gate provided are same. The DIBL value obtained is 75.98 mV/V, the sub-threshold slope is 62.32 mV/decade and the ION and IOFF ratio obtained is 4.86 × 109. From the result it is observed that sub-threshold slope is decreased by 1.61%, the ION and IOFF ratio is increased by 17.08% and DIBL is decreased by 4.52%. The dimensions of the device are gate work function is 5.2 eV, front gate oxide thickness is 1 nm, back gate thickness is 1 nm, silicon substrate thickness 5 nm, doping concentration ND is 1019 to 4 × 1019 cm–3, and channel length L is 20 nm. Fif. 20 presents a dual metal gate with a short channel having recessed source and drain silicon on insulator MOSFET.
This device provides high ON current, low DIBL value. The channel region is lightly doped and the drain and source region is heavily doped. Work-function of control gate (ΦM1) is 4.8 eV (gold), work-function of screen gate (ΦM2) is 4.6 eV (molybdenum), doping of the channel (Na ) is 1015 cm–3, doping of source and drain (Nd) is 1020 cm–3, doping of substrate (Nsub) is 1015 cm–3 , oxide thickness of channel (tox) is 1.5–4 nm, thickness of buried (tbox) is 100–300 nm, thickness of recessed is (trsd) 30– 100 nm, length of recessed (dbox) is 3 nm, length of the channel (L) is 30–300 nm. 4. Performance comparison and discussion the performance comparison of different double gate MOSFET has been shown in Table 1 for sub 20 nm technology node including their applications. Since multiple gate MOSFETs have more control of gate over the channel, therefore different DG MOSFET have been considered for performance comparison. Metal gates with high work function are suitable for low OFF-state leakage. The underlap asymmetrical gate increases fringing electric field and leads to better ONstate transistor performance. The absence of depletion region between source/channel and drain in junction-less transistor, improves transistor current drive capability by increasing ON-state current. The high-K dielectric material is preferred as oxide region under gate to improve sub threshold performance parameters and improved switching behavior of transistor. The comparison 20 nm junction less double gate (JLDG) MOSFET provides the lowest sub threshold slope and maximum ION/IOFF ratio. The lowest DIBL obtained from graded channel dual material gate junction less (GC-DMGJL) with channel length 15 nm . Therefore, multi-gate juntionless transistors with low leakage and good ION/IOFF ratio can be preferred as low power digital and memory applications. Several researchers have explored bio-sensing ability of double gate MOSFET by including Nano-gap cavity region. The dielectric constant of these cavity regions depends on changes occurred in bio species that adds to a very interesting feature to the biomedical applications of these devices.
Table 1 Resemblance among different structures of MOSFET
|ION (A/μm)||IOFF (A/μm)||ION/IOFF||SS (mV/dec)||DIBL (mV/V)||Channel length (nm)||Application|
|7.695 × 10–4||3.741 × 10–10||2.057 × 106||73.42||21||15||Analog circuit|
|127 × 10–4||1 × 10–15||1.27 × 105||68||65||20||Digital circuit
|(DMSG) MOSFET –
|___||___||1.053 × 10–16||64.7978||___||10||Digital circuit|
|–||–||4.86 × 109||62.32||75.98||20||Analog/RF|
|DGJL MOSFET||–||–||4.03 × 109||63.34||79.58||20||Analog/RF|
Different structures of MOSFET have been investigated with their basic subtleties and measurements including applications. Alteration in the structure of MOSFET has been done for the most part to lessen the short channel impacts that incorporate DIBL and SS esteems. The fundamental thought process of these structures is to build the ON-state current and decrease the OFF-state current. The MOSFET structures are additionally examined for reasonable simple/RF execution boundaries to get an ideal scope of Tran’s conductance, transistor gain, security factor and basic frequencies. The examinations between various structures are done based on sub threshold and simple/RF execution boundaries. According to correlation made, the junction less twofold entryway (JLDG) MOSFET gives the most reduced sub threshold incline and greatest ION/IOFF proportion for channel length 20 nm. The least DIBL got from evaluated channel double material entryway junction less with channel length 15 nm. Door built transistors of high work metal contact with different high-K dielectric districts are discovered appropriate to acquire improved sub threshold execution. This shows door built multi-entryway functionless MOSFET can possibly meet future scaling patterns with expanded similarity in CMOS innovation for any computerized/simple and compact IoT or biomedical applications.