# Biasing of JFET: Gate Bias, Self Bias, Voltage Divider Bias, Source Bias, Current Source Bias

Table of Contents

**Biasing of JFET:**

We know that the input resistance of a JFET is quite high compared to a bipolar transistor. Therefore, it should inculcate in mind that at the time of JFET biasing, its input resistance should in no way get lower. Therefore, for the achievement of this objective, the gate-source diode of a JFET is always revere-biased. Thus, negative V_{gs} is required for biasing an N channel JFET, whereas positive V_{gs} is needed for biasing P channel JFT. Contrarily, if the gate-source of JFET is forward biased instead of reverse bias, its high input resistance will drop suddenly. Thus, this device will lose its advantage due to which it has a preference over a BJT.

A JFET can be biased in the ohmic or active regions. When it is biased in the ohmic region, it is equal to the resistance. However, when it is biased in an active region, it becomes equivalent to a current source.

The methods commonly used for JFET biasing are as follows:

1). Gate Bias

2). Self-Bias

3). Voltage Divider Bias

4). Source Bias

5). Current Source Bias

## Gate Bias

In this method of biasing, the negative gate voltage (-V_{gg}) is provided to the gate through biasing resistor (R_{g}), while the source of JFET is earth (figure 5.18 a). In this method, as the bias voltage is supplied on the JFET gate, therefore, this method of biasing is called gate biasing. Drain current sets up due to providing a negative bias voltage to the gate, the value of which is lower than I_{dss}. When this drain current passes from R_{d}, drain voltages are generated parallel to it, values of which are as below.

V_{d}= V _{dd}– I _{d} R_{ d}

This method of JFET biasing in an active region is quite unpopular because point Q becomes highly vulnerable/unstable due to gate biasing. However, the method is preferred for biasing in the ohmic region instead of the active region, because, the issue of stability of the Q point does not arise in the ohmic region.

Figure 5.18 (a). Gate bias (b). Q point unstable inactive region (c). biased in the ohmic region (d). JFET is equivalent to resistance

In figure (b) minimum and maximum trans-semiconductor curves of a JFET 2N5459 have been shown while operating its inactive region. In such a situation, I_{dss }value varies between 4-16 mA, and V_{gs (off0 }value varies between-2 to -8. If the gate bias value of this JFET becomes -1V, we get minimum and maximum Q points as has been illustrated in the figure. Thus, under such a situation, the drain current of Q_{1 }is 12.3mA and the value of Q_{2 }drain current is just 1mA. In figure (c) a JFET has been shown to be biased in the ohmic region. The upper end of the DC load line is capable of drain saturation, the value of which is as below:

I_{D (sat)}=V_{DD}/R_{D }

Remember, when a JFET is biased in the ohmic region, the value of V_{gs} is retained at zero (i.e. V_{gs}=0) and I_{D (sat)} value is far lower compared to I_{DSS} i.e.

I_{D (sat)}<< I_{DSS}

The equation reflects that the value of drain saturation current has to be significantly lower compared to maximum drain currents’ value i.e. if a JFET’s I_{DSS} value is 10mA, hard saturation results in case V_{gs} value is considered as zero and I_{D (SAT)} value 1mA.

When a JFET is biased in the ohmic region, t is reflected vide a resistance R_{DS }(i.e. JFET is converted to R_{DS}) as shown in figure (d). According to the figure, JFET is fixed in R_{D} series treating JFET equivalent to R_{DS} resistance. Through such equivalent circuits, drain voltages can be calculated. When R_{DS} value is lowest compared to R_{D}, the value of drain voltages approximates zero.

From the above discussion, it has been proved that such type of bias is considered extremely unstable. Its other major defect is that if the biasing value of V_{GS} is other than zero, another or one more power supply will become imminent under the situation. Thus, the application of this biasing method equals almost nothing.

## Self-Bias

In this biasing method, a power supply is just provided on the drain, where no power supply exists on JFET’s gate (figure 5.19). Gate resistor R_{G} does not affect bias at all, because no voltage drop occurs parallel to it. As the gate has been grounded through resistance R_{G}, therefore, the gate remains on zero voltage. The application of R_{GS} for isolating AC signals from the ground is essential while using JFET as an amplifier (Read details in the coming pages). Current source resistance passes through R_{s }due to which voltage drop takes place parallel to R_{s. }Therefore, the voltage drops which occur parallel to R_{s} in this biasing method, perform the function of gate-source voltage.

When source current I_{s }passes through N channel JFET’s source resistance as shown in figure (a), voltage drops form parallel to R_{s, }which makes the source positive with respect to ground. As drain current pass through source resistor R_{s, }and values of source current and drain current are equal (i.e. I_{S}=I_{D}), further as the value of gate voltage (V_{g}) is zero_{, }thus, in this case, source voltage V_{S} equals the product of drain current and source resistance (R_{S})i.e. V_{S}=I_{D} R_{S}. However, the value of gate to source voltage is as under:

V_{GS} =V_{G} -V_{S}=0 – I_{D}R_{S}

V_{GS} = -I_{D} R_{S} …… (N-Channel)

According to the equation, it is evident that gate-source voltage equals the negative voltage found parallel source resistor. Basically, this circuit generates bias for itself via providing reverse bias to the gate as a result of negative voltages produced parallel to R_{S. }In the case of P-channel JFET, the current passing through R_{S}, causes a negative voltage on the source (as shown in figure b). Thus, the value of V_{GS} is as follows.

V_{GS} = +I_{D} R_{S} ……. (P-Channel)

Drain voltage value with respect to ground is as under

V_{D} = V_{DD}-I_{D} R_{D}

As, V_{S} = I_{D} R_{S}, thus, drain to source voltage equals the following

V_{DS} = V_{D} – V_{S}

Entering the values of V_{D} and V_{S} in the above equation

V_{DS}= V_{DD}-I_{D} R_{D}-I_{D}R_{S}

V_{DS}= V_{DD}-I_{D} (R_{D}+R_{S}) …(N-Channel)

V_{DS}= -V_{DD}+I_{D} (R_{D}+R_{S}) …(P-Channel)

Remember, self-biasing also works as feedback. When draining current increases, source current also increases (as I_{S} = I_{D}), due to which drop in R_{S} also increases. As this bias provides reverse bias voltage to gate-source diode, therefore, reverse bias on gate-source diode also increases with an increase in drop parallel to R_{S}. which results in lowering drain current. As the Q point in self-biasing is not so stable compared to other biasing methods, therefore, only small-signal amplifiers are self-biased, whereas, for high signals, other types are used for biasing a JFET. Self-bias JFET circuit is mostly used on the front part of communication receivers (where a small signal exists)

**Voltage Divider Bias**

In this biasing method, Thevenin voltages are supplied to the gate by fixing two resistors on the gate. In diagram 5.20, a voltage divider bias circuit has been shown. As its name suggests, the value of bias voltage or gate voltage is reduced to such an extent by dividing it into two parts with the help of two resistors, that their value remains a fraction compared to supply voltage (i.e. gate voltage is equalized just to a fraction of supply voltage)

According to the diagram, gate voltage (V_{G}) is set through R_{1} and R_{2}, values of which according to the voltage divider formula is as follows:

V_{G} = V_{1h} [R_{2}/R_{1}+R_{2}] V_{DD}

Thus, we get the following voltage parallel to the source resistor or between ground and source.

V_{S}= V_{G} – V_{GS}

As VGS is negative, therefore, source voltages are relatively higher as compared to the gate voltage. When source voltages are divided by source resistance, we get drain current (which is equal to source current) i.e.

I_{D} = V_{G} -V_{GS} /R_{S} = V_{1h} -V_{GS}/R_{S}

If the value of V_{GS} is higher significantly relative to V_{G} or V_{ih}, the drain current of nearly every JFET normalizes as shown in diagram 5.20 b). However, as V_{G} varies extensively from transistor to transistor, therefore, I_{D} might have various possible values. Remember that voltage divider bias can establish a strong Q point due to the presence of large gate voltage compared to V_{GS}(the middle point of intersection between a straight line and trans-conductance curve, is called the Q point). Although voltage divider bias is more stable as compared to self-bias, nonetheless, this method of biasing is not so balanced as compared the bipolar transistor.

For clarification, separate voltage divider bias circuits of N-channel and P-channel JFET have been shown in diagram 5.21.

**Source Bias**

The source bias method is applied for eliminating variations in V_{GS} as far as possible (this biasing method is also called two supply source bias). In this method, V_{SS} value is increased excessively as compared to V_{GS}. In figure 5.22, a source bias circuit has been illustrated. Practically, the value of drain current will be as follows

I_{D} = V_{SS} – V_{GS}/ R_{S}

In a typical situation, drain current is achieved by dividing supply voltage (V_{SS}) by source resistance (R_{S}). i.e.

I_{D}= V_{SS}/ R_{S}

Under such a situation, the value of drain current remains almost constant despite changing JFET and temperature. As V_{SS} value is much higher relative to V_{GS} (which normally remains between -1V to -5V), therefore, comparatively better results can be achieved through source bias.

**Current Source Bias**

In current source bias, a bipolar transistor functions as a constant current source for generating a fixed value of drain current. When the drain supply voltage is not too large, a suitable gate voltage value also does not exist for avoiding variations in V_{GS}. In such a situation, the designer prefers the application of current source bias 9its circuit displayed via diagram 5.23 a)

A bipolar transistor has been used in the circuit, on the emitter of which, bias is supplied. Thus, a fixed current pass through JFET. Therefore, the value of drain current in such a situation will be as under.

I_{D} = V_{EE}-V_{BE}/ R_{E}

As junction transistor works in the capacity of the current source, therefore, it strives to equalize JFET drain current to its collector current (i.e. I_{D} = I_{C}). In the case of a constant I_{C} value, the drain current value also remains constant. Thus, the impact of variations on V_{GS} due to current source bias becomes ineffective and consequently, JFET operates in a balanced manner.

In figure (b) it has been shown how effective current source bias is. According to the diagram, despite different V_{GS} values for each Q point, both Q points have the same current capacity. It implies that there is no worthwhile impact of V_{GS} on the value of drain current. Thus, compared to other biasing methods, current source biasing forms the most stable Q points because drain currents’ value stays uniform in spite of variations in JFET characteristics.

**Uses of JFET**

Junction Field Effect Transistor is mostly applied as amplifiers and analog switches. Therefore, these are commonly used in multiplexors, chopper amplifiers, buffer amplifiers, voltage controller resistors, automatic gain control (AGC) circuits, cascade amplifiers current sources, and current limiters.

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