JFET: Junction Field Effect Transistor Construction and Working

(Last Updated On: May 6, 2022)

Junction Field Effect Transistor (JFET)

A FET with a PN junction between its gate and channel is called junction FET(Field Effect Transistor). This is the first form of FET which is simply known as JFET(Junction Field Effect Transistor). In other words, a transistor with two PN junctions on opposite sides of its channels is called JFET. Its input resistance is very high and reverse bias is supplied on its gate. There is an arrow sign on its electrodes’ gate. If the arrow sign is towards the gate, it is N channel JFET and if its direction is outward, it is P channel JFET (figure 5.9)

Figure 5.9

Construction of JFET:

A JFET(Junction Field Effect Transistor) is fabricated alongside an N channel or P channel (although an N channel is normally preferred). For devising an N channel JFET, first, a narrow bar of N-type semiconductor material (usual silicon) is taken. Then, two P-type junctions are diffused on opposite sides in the middle part of the N bar (figure a). These junctions construct two P-N diodes or gates and the place located in the center of the gates is called a channel. Both P regions are interconnected internally and a single wire just out from it, which is called a gate terminal. On both ends of the bar, two ohmic contacts (or direct electrical connections) are fixed. One of these contact leads is called source terminal S while the other one is drain terminal D. When potential difference forms build up between drain and source, current passes through the channel located in the middle of the P region on the bar. The current contains the majority of carriers (In the case of the N channel, the majority of carriers are electrons).

Figure 5.10

The basic construction of an N-type JFET(Junction Field Effect Transistor) has been described more explicitly in diagram 5.11. In its simplest form, an N-type channel JFET is made up of an N-type silicon bar (figure A) on both points of which two metal contacts have been fitted, called source and drain. P-type region’s doping is done on both sides of the center of bar (figure B). Metal contacts are fitted alongside both these P regions, which are called gates. Normally, the leads of both gates are inter-connected (figure C). The region between source and drain is known as the N channel (figure C). As two PN junctions (diodes) are formed via P-type gate regions and N channel (one of the junctions formed by gate and source whereas another one by the gate and drain), it is therefore called transistors’ junction FET(Field Effect Transistor)

Figure 5.11

The construction of P channel JFET(Junction Field Effect Transistor) is also almost similar to an N-type JFET. The only difference is that a P-type bar is used in P channel JFET, with two N-type junctions formed on both sides of the middle of this bar (figure 5.10). However, it should be remembered that holes are the majority carriers in P channel JFET which pass through the channel located between two N regions or gates. The FET terminal through which the majority of carriers intruded into the bar, is called the source. And the terminal through which the majority of carriers move away from the bar, or the terminal through which the majority of carriers emit, is called the drain. Whereas, the FET terminal on which voltage or electric field is supplied and through variations in which, the conductivity of a channel is changed, is called the gate.

Working  JFET:

The following points should be in mind for understanding the working of a JFET(Junction Field Effect Transistor)

1). Gates is always reverse biased. Therefore, the gate’s current IG is practically zero. 0…

2). Source terminal is always connected with that end of a drain supply, which furnishes necessary charge carriers. In an N channel FET, source terminal S is connected (for receiving electrons) with the negative end of the drain voltage supply. While in a P channel FET, the source is connected with the positive end of the drain voltage supply (for receiving holes flowing through the channel).

As soon as the circuit gets the drain supply voltage, free electrons start moving from the source towards the drain. These free electrons pass through a narrow channel located in the middle of the depletion region, the width of which is controlled by gate voltages. The width of the channel decreases by supplying high negative voltages on the gate. As a result, channel’sresistance increases, and the value of the drain current subsides.

Now, by means of biasing an N-type JFET channel, we discuss its working of N via changing VGS or VDS or both.


The biasing of an N channel JFET(Junction Field Effect Transistor) has been demonstrated in figure 5.12. According to the diagram, a battery (which provides voltage parallel to gate and source) VGS has been fitted for supplying reverse bias voltage. These voltages, develop electric fields, which results in the formation of a depletion area. Another battery VDS has been fixed between the drains and the source. So that electrons present in N-type material could move towards the positive potential of drain D, passing through a channel fitted in the center of both P gates. As P gates are directly associated with the N block, thus two PN junctions are formed. This’s the reason the transistor is called junction FET.

Figure 5.12

Remember, during normal FET operation, current always flows from source to drain in the N channel. This current is denoted by ID. Thus, in order to ensure the flow of current from source to drain, drain D is positively biased with respect to source S viaVDS (i.e. it is connected with the positive terminal of the battery) and gate G is negatively biased with respect to source S viaVGS(for simplicity and ease, a lead has been shown towards the gate. Suppose this lead consists of two gatesother leads interconnected together) Thus, two PN junctions are fitted reversed bias from the gate towards the channel so that zero current could basically pass through the gate lead. During a normal JFET operation, gate-source voltage (VGS) is never used for forward biasing a gate-source PN junction (i.e. gate is always supplied negative bias with respect to source or gate-source PN junction is always reverse biased), so the value of gate current remains zero. That’s the reason input resistance of such a transistor is very high (usually even higher than 1000 megaohm)

In the case of P channel JFET, As gate is of N-type, therefore, VGS is positive whereas VDS is negatively biased. (That’s entire polarities of a P channel JFET are reverse compared to N channel JFET, although both operate in a uniform manner). In figure 5.9, suitable polarities with respect to P and N channels JFETs circuit symbols and source terminals, have been illustrated.

Depletion Region

A depletion region is an area or territory, where charge carriers almost do not exist (or the region, which is depleted of charge carriers is called a depletion region). In the case of N channel JFET, as P gate regions are heavily-doped compared to an N block, therefore, depletion region expands between every P gate to the interior of the N channel, as has been manifested via a white space along with the P gate in the figure 5.12. In other words, due to the reverse biasing of the gate-channel junction, depletion regions are made-up of junctions. As a result, the channels’ conduction portion of the area passing the majority of carriers becomes smaller. Due to the presence of these depletion regions, the channel gets narrower (or its area decrease) while channel resistance increases, normally these depletion regions are wedge-shaped i.e. from the drain end side, they are spacious and from the source end side, they are narrow. This happens at the drain end due to high gate-to-channel reverse bias (as the drain has been provided with a positive bias). Depth of a depletion region’s channel depends on this reverse bias which keeps on changing via variations in VGS and VDS. Thus, channel resistance and channel current also change with respect to VGS, and VDS or Vgs bias is enhanced too much, the depletion region inside the N channel will enlarge very excessively. Due to this, the electrical resistance of FET becomes very high thus, electrons flow or currents ‘value passing through the channel will decrease significantly (Remember, due to reverse bias, very low leakage current can pass through the gate. It is because FETs gate or input resistance is very large). In brief words, depletion region operates as an insulator, due to which it becomes narrow and ID reduces. When the negative gate bias voltage is increased further, edges of depletion region combine through the center of channel, and ID stops/cut off completely, thus, FET’s gate controls drain current. Remember, this drain current contains just one kind of charge carrier (electrons in the case of the N channel and holes in the case of the P channel). That’s the reason, FET is called a unipolar device. In the figure, 5.13 different forms of depletion regions have been shown, which arise out of changes in gates’ bias voltage.

figure, 5.13

Control of Id by Changing the Values of Vg

Current passing through a JFET’s channel can easily be changed by changing the values of gate voltage. That’s why a JFET(Junction Field Effect Transistor) is called a voltage control device instead of a current control device. In other words, the current passing through the channel can be controlled through gate voltage. In case of a large negative gate voltage, the current flowing between drain and source will become less. This phenomenon can very clearly be clarified through the study of specific drain curves in figure 5.14. Every curve here reveals how does drain current Id changes with respect to Vdsat a specific gate-source Vgs voltage value.

Figure 5.14

When Vgs and Vds both are zero

In such a situation, drain current Id is zero, because Vds is zero. The thickness of the depletion region formed around the PN junction is equal and uniform from all sides. 

Figure 5.15

When Vgs Value is Zero and Vds Value is Increased from Zero

First of all, we assume that the Vgs value is zero i.e. gate is short with the source. The shape of Vgs has been shown through the topmost curve in figure 5.14. In such a situation, when the value of Vds is increased above zero, drain current Id increases almost in a straight vertical line until its value becomes 6V (this value has been depicted by point A in the figure). Meanwhile, channel resistance (under ohm law) almost remains constant, that’s why this operational region is called an ohmic region. Practically, it has been explained in figure 5.16 (A), in which we can see wedge-shaped depletion regions. Channel width visible on source end Ws is larger in width compared to channel width Wd on the drain side because gate-drain reverse bias is greater than gate-source reverse bias. As soon as Vds value increases, Wd becomes narrower. Thus, channel resistance gradually increases. Therefore, a curve that is formed between Id and Vds starts tilting step by step due to an increase in Vds.

Id keeps increasing due to an increase in Vds until the value of drain current becomes constant after Vds reaches a specific value Vds, called pinch-off voltage. This maximum value of drain current is called Idss. In Idss, ss means that at this value, in order to make Vgs zero, gate has become short with the source. This current is also called zero gate voltage drain current. In the diagram, the Vgs=0 curve implies that after reaching 9.2mA, the drain current value stops increasing when the Vds value becomes 15V. (until the reverse breakdown of gate-drain junction occurs) The middle region of point A and the breakdown region is called the pinch-off region and here Id almost remains constant.

In other words, when depletion regions recombine as a result of gate-drain reverse voltage, the value of Id becomes constant in the region. It is called the pinch-off region and the voltage value, on which this operation takes place, is called pinch-off voltage (Vp). As every bipolar transistor has a specific (β) value, every JFET also have a similar specific value (Vp). In the case of a zero Vgs value, the drain current flowing through the pinch-off region is represented by a special symbol Idss. In diagram 5.14, the value of Idss has been given as 9.2mA and this is the maximum current value flowing during normal operation. Remember, every FET has a specific Idss value i.e. the β value of every bipolar transistor is different, exactly the same way Idss value of every JFET(Junction Field Effect Transistor) is also different.

Looking at the topmost curve Vgs=0 in diagram 5.14, it can be understood that when the Vds value is 35V, reverse breakdown occurs at the gate-source junction, due to which Id increases at a dangerous brisk speed. Entrance into this region usually refrains.

In figure 5.16 (B), the pinch-off region has been shown in a simple way. As soon as Vds increases above 6V, depletion regions at the channel drain end, recombine and render the channel pinched-off. (i.e. Wd=0). With this, there arise a possibility of drain to source current getting lower and coming down to zero. However, electrons coming from source terminal, pass through the channel and when they enter the pinch-off region, their passing speed from the depletion region increases due to Vds potential. Thus, due to the attraction of Vds potential, these electrons reach the drain terminal. Thus, Ids value does not come down to zero, rather it becomes constant with an increase in Vds. However, it has to be membered that pinch-off does not imply cut-off, in fact, the Id value is maximum at pinch-off.

figure 5.16

Various cases show effects of VGS and VDS on the shape of the channel, and size of the drain current

When Value of Vgs is -1V i.e. Vgs=-1V

If the gate is made reversely biased with respect to source through supplying -1V, the behavior of FET becomes quite consistent, with the exception that the value of drain current starts diminishing due to lower Vds value. Analyzing the Vgs curve of -1V, one can understand that at point B where the Vds value is 5V, Id starts reducing and ultimately stops increasing at 6mA. In other words, the pinch-off region starts at Vds=5V instead of Vds=6V (while Vgs value was zero volts), because supplying one-volt reverse bias on gate requires 5V drain voltage. Vgs=-1V curve forms lower on the side compared to Vgs=0 because depletion regions penetrate further into the channel due to the 1V reverse bias on the gate source. Thus, channel resistance increases and the drain current gets lower further.

In diagram 5.16 this pinch-off status at Vgs=-1V has been shown. It becomes clear viewing the diagram that when the value of Vgs was zero-volt, the present channel width size is smaller compared to the one being built from the source end at that time. When the value of Vds increases past 5V, the channel on the drain end gets pinched off and compared to Idss, the current stops at a lower value (6.3mA) because the channel narrows down further as a result of the gate-source being reverse biased.

Other Values of Vgs

In figure 5.14, Vgs=-2V reveals that Id increases till point C, where value of Vds is 4V. Afterward, this curve bends and starts representing a constant value of Id. When value of Vgs is -3V, Id increases till point D (where Vds value is 3V). Similarly, with increasing negative values of Vgs, values of Id become smaller (i.e. Id curves gradually lowers down as a result of increasing negative Vgs values further) until when Vgs value is -6V (i.e. Vgs=-6V), Id curve becomes exactly flat, which reflects zero value of Id. Actually, Id for all values of Vds will become zero in case of increasing the Vgs values to -6V or higher (until breakdown occurs). Its reason being the gate reverse bias value is so high under the situation that the depletion region pinches off the entire channel. Thus, channel resistance increases enormously, and resultingly, channel current cuts off completely (i.e. flow of current from the channel stops completely). This region highlighting characteristics of the Field Effect Transistor is called a cut-off region. The status of this cut-off region has been shown in diagram 5.17. Remember, the Vgs value, on which this cut-off situation occurs, is also denoted as Vgs(off).

figure 5.17


The summary of detail is as under

(i). After fixing the Vgs value (zero or negative), as the value of Vds is increased, initially Id value increases until the channel is pinched-off and Id value almost becomes constant. And increasing Vds values further will ultimately cause a breakdown on JFET(Junction Field Effect Transistor), after which Id value gets extensively high (such a situation is normally avoided).

(ii). Through fixing Vgs on high negative values step by step, values of pinch-off voltage and breakdown voltage also decrease.

(iii). After fixing Vds value, as Vgs values are increased, Id gets lower, until Id value comes down to zero at a specific Vgs value (called Vgs (off).

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