FET as a Voltage Amplifier:
Just like a bipolar transistor, a field-effect transistor can also be used as an AC amplifier for obtaining voltage gain. When this device is used in its pinch-off region, a small change in the gate to source voltage (input voltage) leads to a major change in the drain to source voltage (output voltage). In other words, when gate-source voltages (VGS) of a JFET is changed, change also occurs in the drain current (ID). Changes in ID also cause a change in output voltage VD. Thus, the base of a JFET voltage amplification depends on the control of its gate-source voltage. Through variations in which, drain current is changed or controlled. Thus, changes in drain current can cause a major change in voltage parallel to load(which is fitted in series alongside drain) It is important to have knowledge about trans-conductance (denoted as gm) prior to knowing something about JFET amplifiers because trans-conductance plays an important part in controlling the voltage gain. Thus, trans-conductance can be defined as below:
The mutual ratio of change in drain current (output) to changes in the gate to source voltage (input voltage), is called trans-conductance. i.e.
gm= change in drain current/ change in the gate to source voltage
As changes in ID and VGS result due to voltage current, thus in terms of AC values, the trans-conductance formula may be described as below:
gm = Id/Vgs or id/vgs … mho or siemens
From the above-mentioned formula, the following drain current value is obtained.
Id = gm Vgs or Id = gm Vin
The formula shows that output current Id equals the product of input voltage Vgs and trans-conductance gm. As the current source (value of which is gm Vgs) is a voltage control source (i.e. changing Vgs value changes Id value), thus current generated through the current source depends on Vgs (input voltage)
Remember, for the achievement of high gain, it is necessary that JFET be provided biasing in that region. Where gm value is maximum (i.e. about Vgs=0). In other words, for the purpose of achievement of high gain, JFET should be used along with gm.
A Common Source Amplifier
A common source (CS) amplifier just resembles a common-emitter BJT amplifier, therefore, a number of things are common between these two. For the purpose of voltage amplification, a common source circuit is most vastly used compared to the rest of the circuits.
In figure 5.24 (a), a common source amplifier circuit consisting of voltage divider bias, and in figure (b) its equivalent circuit has been shown. Coupling capacitors have been used on circuits input and output which work as an AC short circuit (i.e. only AC signals pass through it). That’s why AC input has been coupled directly with the FET gate. A capacitor fixed parallel to RS, is a bypass capacitor, which also functions as a short. As the source has been bypassed with the ground through this bypass capacitor, therefore, entire input voltage combines between gate and source, through which AC drain current generates. In other words, an AC signal is provided on the gate, and the output signal is received on the drain. As drain current passes through drain resistor, its value equals gm Vin, therefore, an amplified AC signal is produced on output. Remember, AC output voltages received through a common source JFET amplifier (just like AC voltage received through a common emitter BJT amplifier) are 180° out of phase (i.e. inverted output received through such amplifiers). The output signal is subsequently coupled with load resister through a coupling capacitor fitted on output (figure a)
When the input voltage is either increased or decreased, changes occur in Vgs, due to which drain currents’ (Id) levels also increase or decrease respectively. Likewise, due to changes in ID, voltages parallel to drain resister RD drop. As a result of this change in VRD, amplified AC output voltages Vo or Vout are accrued. When input voltages move in a positive direction, negative gate sources (-Vgs) voltage lessens. Due to this reduction in -Vgs, ID level increases. Consequently, voltage drop parallels to RD increases. As shown below
Thus, as a result of an increase in ID, a drop occurs in drain voltage or output voltage. Thus, as input voltage move in a positive direction, output voltage moves in a negative direction. Just exactly, when input voltage Vi moves in a positive direction, ID level decreases owing to addition in -Vgs. As a result, the drop parallel to RD minimizes. Thus, going positive, output voltages are produced. Thus, the output voltage of this amplifier is 180° out of phase with respect to the input voltage. Phase relation has been shown in figure 5.25
In other words, when a negative-going signal is provided on input, then
i). Gate bias increases
ii). Depletion region expands
iii). Channel resistance increases
iv). ID gets lower
v). Drop parallel to RD decreases
vi). Resultantly, there is a positive-going signal on the output
When a positive-going signal on input is provided, the negative-going signal on output is received. It implies that phase inversion exists between the input signal given on the gate and the output signal received on the drain. In figure 5.24 (b), an equivalent circuit parallel to this amplifier has been revealed. As AC input voltages appear between gate and source terminals, therefore, the value of the current source equals gm Vin. This AC drain current passes through the AC drain resistor.
The input impedance of a common source amplifier (Zin) equals the RGS parallel total of R1║R2, as is evident from the equivalent circuit shown in figure (b). When the RGS value of a typical JFET is extremely large, the input impedance of a common-source amplifier will be as follows.
Zin= R1║R2= R1xR2/R1+R2
Output impedance (Z out) equals a parallel total of RD and RL i.e.
Z out = RD║ RL = RD x RL/RD + RL
As RD value is extremely high at the pinch-off region, therefore, Z out value usually equals the following
Z out = RL … if RD ˃˃ RL
The ratio between output AC voltage and input AC voltage is called voltage gain. i.e.
A ν = V out/ V in … (1)
In case of JFET as Vgs = Vin and V ds = V out, then
A ν= V ds / V gs … (2)
When output current passes through AC drain resister Rd, output voltage value under the situation will be as below.
V ds= Id Rd … (3)
We know that Id = gm Vgs
Entering value of Id in equation (3)
V ds= gm. Vgs. Rd … (4)
If equation (4) is divided by Vgs, then
V ds/ V gs= gm. Rd … (5)
As the ratio between an input voltage and the output voltage is called V gs voltage gain, the following gain value is attained from JFET.
A ν = gm. Rd … (6)
It is evident from the above-mentioned equation that a common source JFET’s amplifier equals AC drain resistance’s trans-conductance times or equal to the product of AC drain resistance and trans-conductance. As lower voltage gain is achieved through a common source circuit (only ⅒times compared to common emitter bipolar transistor circuit) and distortion also exists in its output, therefore, usage of this circuit is comparatively less. However, the biggest advantage of the circuit is that its input impedance is maximum due to which the amplifier circuit is used as an impedance matching circuit between a high impedance signal and a low impedance signal.
In figure 5.26, a common source JFET amplifier circuit containing self-bias has been displayed instead of a voltage divider bias. Complete detail about the circuits has already been described above. However, input and output impedances’ values in the case of the self-bias circuit are as follows. The input impedance of such a circuit equals a parallel combination of RG and RGS.
Z in= RG║RGS = RG x RGS/RG + RGS
As the RGS value of a typical JFET is inordinately high, therefore, the input impedance of a self-bias common source amplifier input will be equal to the following i.e.
Z in= RG
Whereas output impedance equals a parallel combination of RD and RL
Z out= RD║R1
Z out= R1 … if RD ˃˃R1
Common Drain Amplifier or Source Follower
As low voltage gain is generated through a common source amplifier circuit, and distortion also occurs in its output, therefore, keeping in mind the defects of a CS circuit, a common drain amplifier circuit is used. A common drain circuit is also called a source follower circuit. This type of circuit has been depicted in diagram 5.27
Output voltages are found parallel to source resistor RS in a common drain circuit. Outer load resistor RL is coupled with FET’s common source terminal and gate bias voltage VG is obtained through VDD with the assistance of R1 and R2 potential dividers. Thus, the circuit has exerted potential divider bias. Neither a resistor is fixed along with a drain terminal in a series nor any source bypass capacitor i.e. drain terminal is connected directly with supply voltage VDD. Input signal tends to operate the gate. Whereas the output signal is coupled with the source through the load.
Just like an emitter follower, the voltage gain of a source follower is also less than unity. The greatest advantage of this circuit is that its resistance is too high. Due to this reason, often source followers are applied at the start of a system which is followed by voltage gain’s bipolar stages (remember, that JFET’s voltage gain is less than BJT’s voltage gain, however, its input resistance is greater than BJT. That’s why the advantage of FET’s high input resistance is availed through fixing it at the beginning of a multi-stage amplifier and high voltage gain results through fixing BJT subsequently. Thus, maximum advantage can be obtained through the shared application of FET and BJT). Remember, this circuit is comparatively more popular. For the understanding operation of a common drain circuit, it must be inculcated that VGS ‘s value remains constant, the value of source voltage Vs equals (figure 5.28)
VS = VG +V GS
When the signal is provided on a FET’s gate through input capacitor C1, an increase or decrease occurs respectively in VG depending on whether the signal is positive or negative, however, VGS remains constant. For instance, if an increase of 0.5 V in Vi, source voltage Vs also increases by 0.5V approximately. Similarly, when input is -0.5V, VS also reduces by about 0.5V. As FET’s source terminal also happens to be its output terminal, therefore, output voltage procured through a common drain circuit nearly equals the input voltage. That’s the reason, the voltage gain of a common drain circuit is called unity (however, practically there is a small difference between V1 and V0)
As output voltages on a JFET’s source terminal are changed through the signal voltage provided on the gate, therefore, a common drain circuit s also known as a source follower. The input terminals of this circuit are the drain and gate, while the output terminals are the source and drain. Thus, the drain terminal is common between input and output terminals, or input and output signals are applied with respect to the drain (which is grounded). Thus, such a terminal is known as a common drain or ground drain. However, it has to be remembered that in biasing this circuit, the self-biasing method is also used besides the voltage divider bias method (figure 5.29)
AC source resistance value of a common drain circuit is as follows:
Rs = RS x RL/ RS + RL
I). Voltage Gain
We know that like the rest of the amplifiers, the voltage gain of this amplifier also equals A ν= V out/ V in. The output voltage value of this circuit Vout equals Id Rs and the input voltage value equals Vgs + Ids. As depicted vide diagram 5.30, the gain to source voltage equals
A ν= Id Rs/ Vs +Id Rs
Entering values of Id in the above equation (i.e. Id= gm Vgs)
Aν = gm Vgs Rs/Vgs +gm Vgs Rs= gm Vgs Rs/ Vgs (1+gm Rs)
Cancelling Vgs, following conclusion can be attained
Aν = gm. Rs/ 1+ gm + Rs
The input impedance of the source follower is as below
Zin = RG … self-bias
Zin =R1║R2 …voltage divider bias
iii). Output Impedance
The output impedance of source follower w.r.t Rs is extremely low. Its formula is as below
Zout = Rs/ 1+gm Rs
In the above voltage gain equation, as the divider’s value exceeds the multiplier’s value, therefore, voltage gain always remains less than unity. Besides, output voltages are located on the source, therefore they are in-phase with gate voltage/ input voltage. Due to its high impedance ratio, the common drain amplifier is very useful for application as an impedance matching circuit between a high impedance signal and a low impedance load.
Common Gate Amplifier
To a great extent, a common gate FET amplifier resembles a common base BJT amplifier. Like a common base (CB) amplifier, common gate (CG) amplifier input resistance is very low. As a common base source and common drain amplifier,’ input resistance is very high, as such common gate amplifier is different. In figure 5.31 (a), a common gate amplifier circuit and in figure (b) its parallel circuit has been illustrated.
According to the diagram, FET’s gate has been fixed to the ground. The input voltage signal is coupled with the FET source terminal through signal capacitor C2, whereas the outer load resistor RL is coupled with FET’s drain terminal through load capacitor C3. Another capacitor C1 has been fixed on the gate terminal or ground AC short. As the gate shorts through the ground, therefore entire FET’s source input voltages are generated parallel to the gate-source terminal. Remember, the circuit shown in diagram (a) contain potential divider bias. As Vi are provided parallel to FET’s source and gate terminals (as clear from common gates’ equivalent circuit shown in the figure) and V0 are obtained through drain and gate terminals, therefore, this circuit is the common gate and sometimes grounded gate due to a common gate both between input and output.
We know that the input resistance of a common source and common drain amplifier circuit is very high (because they have a gate input terminal). Contrarily, the input resistance of a common gate fixed on a series circuit (in which the source is the input terminal) is extremely low. This has been explicated with the help of the below-mentioned steps. Input current or source current of a common gate circuit is equivalent to the drain current i.e.
Iin = Is= Id=gm Vgs
While circuits’ input voltages are equivalent to Vgs i.e.
Thus, input resistance value on source terminal is as under
Rin (source)= Vin/Iin= Vgs/gm Vgs= 1/gm
For example, if the value of gm is 4000 siemens (µ), then
Rin (source) = 1/4000µ= 250Ω
The value of voltage gain produced between source and drain is as follows
Aν= Vout/Vin= Vd /Vgs = gm Vgs Rd / Vgs
Aν= gm Rd where Rd= RD x RL/RD+RL
The above equation obtained from the common gate amplifier is just similar to the equation obtained from the common source amplifier. The only difference is that no phase shift occurs between the common gate amplifier’s input and output (i.e. common gate circuit’s output is in-phase with its input) because positive-going input produces positive going output and negative-going input produces negative output. Remember, that the specific value of a voltage gain received from the common gate circuit is 25.
The circuit has very low input impedance, the value of which is as follows.
Zi = Rs║1/ gm
Remember, such a type of circuit amplifier has slightly limited appreciation due to its low input impedance.
The output impedance of this circuit equals the output impedance of a common source amplifier i.e.
Z0 = RD║ Zd
Where Zd= rd
Thus, a common-gate JFET circuit is mostly used in places where a low impedance source is required to be coupled with a high impedance load. This happens because of its inherited low input impedance and high output impedance. The circuit provides a higher voltage gain compared to a BJT common-base amplifier, whereas its current gain value nearly equals unity.
The JFET As an Analogue Switch
A JFET can also be used as an analogue switch besides amplification. An analogue switch is an electronically controlled device, which transmits or blocks a constantly changing analogue type signal. Alternatively, when JFET operates as a switch, it transmits or blocks a small AC signal. Contrarily, a digital switch is one which keeps switching between two possible levels (low or high) as can be seen vide figure 5.32. The analogue switch is closed or opened through a digital type of input. The open/ close of a switch depends on the nature of the device. Some of the devices close switches due to high input and open switches in situations of low input. Whereas the operation of some of the devices is absolutely inverse. As the signal of an analogue switch is controlled through a digital input, therefore, the analogue switch is also called a digital analogue switch (DAS). Remember, when some JFET is used as an analogue switch, its gate-source voltages are limited to just two values (i.e. zero value or a higher value compared to VGS (OFF). Thus, JFET turns off or on just like a switch operating in the ohmic region or cut-off region.
A JFET can be utilized as an analogue switch as shown in diagram 5.33 It is clear from the figure that an analogue signal (Ʋd) has been connected with RD, where normally a fixed supply voltage (ƲDD) is provided. A Digital signal, which closes or opens a switch, is in the form of gate-source voltage (VGS). VGS value is zero volt (due to which JFET conducts) or it equals Vp (due to which JFET turns off). Switch output voltage (Ʋ0) are such drain to source voltages, the value of which equals Ʋd (when JFET cuts off) or nearly zero (when JFET conducts). Remember, the switching sequence shown in diagram 5.32 is different from the switching order in diagram 5.33 because the switch has now been fixed parallel to load resistance RL. When the switch close (JFET turn on) it shorts out RL very effectively. When the switch is closed (in such a situation JFET cuts off), this short depletes. Remember, when a JFET is applied as an analogue switch, it operates in its voltage-controlled resistance region instead of the pinch-off region.
In diagram 5.34 (a), a JFET shunt switch has been demonstrated. The conduct or cut-off of JFET depends on low and high values of VGS. When VGS are high (i.e. zero volts), JFET operates in its ohmic region. When the VGS value is low, JFET remains in its cut-off status, as is evident from the parallel circuit of the shunt switch displayed in figure (b). During normal operation, a small signal of AC input voltage (less than 100 mV) should be supplied on input. Such a small signal ensures that so long as the AC signal does not reach its positive pack value, JFET will operate in its ohmic region.
When the VGS value is high, JFET operates in its ohmic region, due to which the open switch shown in figure (b) tends to close. As RDS values are smaller compared to RD, therefore, Vout values are far less than Vin. When the VGS value is low, JFET cuts off and the switch displayed in figure (b) opens. In such a situation values of input and output are equivalent (i.e. Vi=Vout). Thus, the JFET shunt switch transmits AC signals i.e. passes it or stops (blocks) it.
In diagram 5.34 (c) a JFET series switch whereas in (d) its equivalent circuit has been shown. When VGS are high, the switch closes and JFET resistance becomes equivalent to RDS. In such a situation, the output nearly matches equal to the input. When the VGS value is low, JFET opens and the Vout value nearly becomes zero. The on-off ratio of the series switch (Vout (max) V out(min)) is higher than the shunt switch, that’s why it has a large use.
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