Demultiplexer or Distributor with circuit diagram and operation
Table of Contents
Demultiplexer or Distributor
Demultiplex means “one into many”. A demultiplexer or Distributor is a logic circuit or device, which consists of one input and a number of outputs. A demultiplexer (which is shortly known as DEMUX), basically operates utterly in contrast to a multiplexer. It obtains from one line and distributes it by the given numbers of output lines, that’s why a demultiplexer or Distributor is also known as a data distributor or decoder. By means of providing control signals, input signals can be transmitted on any output line from amongst entire output lines with the assistance of a demultiplexer. In figure 4.10, a general diagram of a demultiplexer has been demonstrated, which has 1 input signal, “m” control signals, and “n” output signals. Remember that a demultiplexer converts serial data to parallel data, whereas a multiplexer is used to convert parallel data to serial data (i.e. a demultiplexer operates or works completely inversely as compared to a multiplexer). In figure 4.11, data transmission has been illustrated through the application of a multiplexer and a demultiplexer.
Figure 4.10 – demultiplexer
Figure 4.11 – serial data transmission using a multiplexer and demultiplexer
Multiplexer and demultiplexer can also be understood through a single pole numerous positioned rotary switches, as can be seen in the figure 4.12. In this figure, rotary switch represents the function of a multiplexer (i.e. with the help of this mechanical switch, parallel data is converting into serial data alternatively) and the function of a demultiplexer or Distributor has been represented via rotary switch 2, which has been converting serial data to parallel data.
Figure 4.12 – rotary switches act like multiplexers and demultiplexers
Some examples of digital demultiplexers are as under:
74137 … 3 – line -to -8-line demultiplexer or Distributor
74138 … 3 – line – to – 8-line demultiplexer or Distributor
74139 … dual – 2 – line – to – 4 – line demultiplexer or Distributor
74154 … 4 – line – to – 16 – line demultiplexer or Distributor
1-line-to-4-line Demultiplexer or Distributor
In figure 4.13 (a) logic circuit of one input and 4 output demultiplexer has been illustrated, whereas block diagram of this circuit has been depicted in figure (b).
According to this figure, one data input line has been applied simultaneously on all four AND gates. Two data select lines can enable or activate only one gate at a time. Thus, data appearing on data input line, reaches the corresponding data output line via the selected gate. In other words, one word containing two bits S0S1 can select just one gate at a given time, which has to work. In this way, data input passes through the selected gate and reaches the output line. Remember that when any one of the gates is operating or it is enabled, rest of the three gates do not work at that time (i.e. all other gates become disabled during that time).
Figure 4.13 – (a). A one-line demultiplexer
Figure 4.14 – (b). Select lines
Operation of Demultiplexer
The working mechanism of a 1 – line – to – 4 – line demultiplexer shown in the figure (a) is as follows, which can also easily be understood with the help of a table shown in figure 4.14.
- When the value of select lines S0S1 is 00 (i.e. S0 = 0 and S1 = 0), in this situation topmost AND gate receives this quantity as 11 via inverters, due to which this gate connected with D0, gets enabled. In this way, data appearing on data input line is received on data output line via this selected gate (remember output of AND gate is 1 only when all of its inputs are 1). If we study the circuit carefully, it becomes clear that the topmost gate is enabled because both its inputs are 11. In this situation all other low-lying gates remain disabled, because any one input of these gates is certainly zero and due to a zero value of any one input or all inputs of AND gate, it becomes disabled (that’s it is does not operate). As such data passes only from that AND gate in order to reach output line, which is active or enabled.
- When the values of select lines or control lines is 11 (i.e. S1 = 1 and S0 =1), in such a situation, the bottom most gate or gate number 4 operates (because inputs of only this gate are 11 and inputs of any one of the remaining three gates is inevitably 0). This input data passes through this gate and received on output line D3. Remember that rest of the three gates remain inactive or do not operate during that time.
- When value of the select lines is 01, in such a situation according to select lines address, only gate number 2 out of the four gates operates. Whereas other three gates remain disabled. Thus, input data reaches D1 output line after passing through AND gate number 2.
Figure 4.14 – demultiplexer Truth table for 1 – to – 4 – line DEMUX
| E | S0 | S1 | D0 | D1 | D2 | D3 |
| 1 | X | X | 1 | 1 | 1 | 1 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 0 |
- When value of select lines is 01, only gate number 3 is enabled and in such a situation, all other remaining gates do not function. Thus, input data is received on output line D2 passing via this gate. This has been explicated via the truth table.
1-line-to-8-line Demultiplexer or Distributor
As the name suggests, this multiplexer consists of 8 outputs, one inputs and three control or select lines as can be seen in the figure 4.15 (a). One data input line E of this multiplexer has been connected simultaneously with all the gates. These three gates remain enable or work alternately according to the address provided by all 3 select lines ABC. The gate which is enabled, (i.e. gate having all inputs as 111), only that gate lets input data E passes through it to provide it on output data line.
Figure 4.15 – (a). 1 – to – 8 demultiplexer
Operation
In order to operate this type of a circuit, first data is provided on its input line. After this, where ever this data has to proceeded, that address is introduced via control lines or select lines. Suppose, we provide 010 address on the control lines after providing input data. In such a situation, only gate 3 becomes enabled or it operates (because only gate number 3 inputs are 111 after select lines values become 010, and this is a condition for the operation of any AND gate) while rest of the gates remain disabled (because providing 010 address on the select lines, at least one input of the gates, except gate number is inevitably zero). Thus, input data is received on output line D2 via gate number 3. It must be remembered that transmission of input data on output lines depends on the control signals being provided on ABC. According to signals, only one gate out of all can operate at a time, via which input data transmits on output.
Now assume that value of select lines is 110 i.e. ABC = 110. In this case, only gate number 4 operates and input data is transmitted on output line D3. In figure 4.15 (b), function table of this circuit has been demonstrated, with the help of which this operation or process can be understood quite easily.
Figure 4.15 (b) – function table of 1 – to – 8 – line DEMUX
| Data | Select lines | Output lines | |||||||||
| E | A | B | C | D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 1 | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
When ABC = 111, only gate number 3 operates, while in such a situation, rest of the gates remain inactive, resultantly input data transmits on output data line D7 via this AND gate.
74154 or 1-to-16 line Demultiplexer or Distributor
74154 is a type of demultiplexer, which contains one input and 16 outputs. In figure 4.16, the logic circuit of a 1 – 16 demultiplexer or Distributor has been illustrated. The input bit has been represented by D in this diagram. The transmission of this input data bit towards output line data bit depends on the value of control input ABCD.
Figure 4.16 – 1 – to – 16 demultiplexer
The pin diagram of 74154 demultiplexer (1 to 16 demultiplexer) has been shown via figure 4.17, wherein pin number 18 for input data D and pin number 20 to pin number 23 are specified for control bits ABCD. All pins from pin number 1 -11 and 13 – 17 are reserved for output bits Y0 to Y15. Pin number 19 is for strobe, which operate in case of low active input. Pin number 24 and pin number 12 are reserved for VCC and ground respectively.
In figure 4.18, logic diagram of a 74154 has been demonstrated, in which an input data bit (pin number 18) can be seen which works under the nibble control of ABCD. This data bit transmits automatically to output line via the decimal numbered gate which is equivalent to ABCD. The bubble or circle sign above strobe reflects its active low input. As a bubble sign has been drawn on pin number 18, therefore data on input inverts. Bubble sign exists on every output as well, which re – inverts the inverted data received or transmitted via this input. As a result of this double inversion on input and outputs, data passing through 74514 is unchanged.
Figure 4.17 – pinout diagram of 74154
Figure 4.18 – logic diagram of 74154
Operation
When ABCD = 0000, in such a situation top most AND gate becomes enabled, whereas all other AND gates become disabled. Thus, data bit D transmits only towards output Y0 i.e. Y0 = D. Remember that if D is low, Y0 will also be low. However, if D is high, Y0 will also be high, as the value of Y0 depends on the value of D. All other remaining outputs are in low state.
If the value of control nibble changes to 1111, i.e. ABCD = 1111, all AND gates except the bottom gate become disabled (i.e. only the bottom gate operates, and rest of the gates except this one remains inactive). Thus, D transmits only towards Y15 i.e. Y15 = D). In other words, according to the address provided by control lines or select lines selection of this AND gate comes into effect, via which input data transmits and received on output line.
This process can easily be understood with the help of a truth table. When value of control nibble is 0111 i.e. ABCD = 0111, then all AND gates except Y7 gate remain disabled (because 0111 = 0x23 +1×22 + 1×21 + 1×20 = 7) and input data D transmits only output line Y7.
Similarly, when value of ABCD select lines is 1101, i.e. ABCD = 1101, Y13 gate enables, whereas all other AND gates gets disabled (because 1101 = 1×23 + 1×22 + 1×21 + 1×20 = 13). Thus, input data D transmits or received only on output Y13 i.e. Y13 =D
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